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? semiconductor components industries, llc, 2012 august, 2012 ? rev. 1 1 publication order number: ncp729/d ncp729 200 ma ultra-low noise very-low iq, high psrr, ldo linear voltage regulator the ncp729 is a 200 ma ldo suitable to provide clean analog power supply rails for noise sensitive applications. this device features ultra ? low noise performance, high power supply rejection ratio and very good transient response characteristics. very low dropout and very low quiescent current makes this ldo an attractive choice for wide range of battery powered, portable products. current limit and thermal shutdown provide protection during failure conditions. ncp729 is available in 1.06 mm x 1.06 mm chip scale package and it is stable with small 1 f ceramic capacitors. features ? operating input voltage range: 2.0 v to 5.5 v ? fixed voltage options available: 0.8 v to 3.5 v ? very low quiescent current: max. 50 a over temperature ? ultra low noise: 10 v rms from 100 hz to 100 khz ? very low dropout: 86 mv typical at 200 ma ? 2% accuracy over full load, line and temperature variations ? high psrr: 72 db at 1 khz ? thermal shutdown and current limit protections ? stable with a 1 f ceramic output capacitor ? available in 1.06 mm x 1.06 mm 4 ? bump csp package ? active output discharge for fast turn ? off ? these are pb ? free devices typical applications ? pdas, tablets, gps, smartphones ? wireless handsets, wireless lan, bluetooth, zigbee ? portable medical equipment ? other battery powered applications ncp729 in en out gnd off on ceramic figure 1. typical application schematic 1 f v out c out v in c in http://onsemi.com 4 bump csp fc suffix case 568ad xxx = specific device code y = year ww = work week xxx yww see detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ordering information device marking information pin connections en in gnd out a2 b2 a1 b1 (top view) a1
ncp729 http://onsemi.com 2 in out bandgap reference active discharge mosfet driver with current limit thermal shutdown eeprom uvlo enable logic en en gnd auto low power mode figure 2. simplified schematic block diagram table 1. pin function description pin no. 4 ? bump csp pin name description b2 out regulated output voltage pin. a small 1 f ceramic capacitor is needed from this pin to ground to assure stability. b1 gnd power supply ground. soldered to large copper plane allows for better heat dissipation. a1 en enable pin. driving en over 0.9 v turns on the regulator. driving en below 0.4 v puts the regu- lator into shutdown mode. a2 in input pin. a small capacitor is needed from this pin to ground to assure stability. table 2. absolute maximum ratings rating symbol value unit input voltage (note 1) v in ? 0.3 v to 6 v v output voltage v out ? 0.3 v to v in + 0.3 v v enable input v en ? 0.3 v to v in + 0.3 v v output short circuit duration t sc s maximum junction temperature t j(max) 125 c storage temperature t stg ? 55 to 150 c esd capability, human body model (note 2) esd hbm 2000 v esd capability, machine model (note 2) esd mm 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. refer to electrical characteristis and application information for safe operating area. 2. this device series incorporates esd protection and is tested by the following methods: esd human body model tested per aec ? q100 ? 002 (eia/jesd22 ? a114) esd machine model tested per aec ? q100 ? 003 (eia/jesd22 ? a115) latchup current maximum rating tested per jedec standard: jesd78.
ncp729 http://onsemi.com 3 table 3. thermal characteristics rating symbol value unit thermal characteristics, 4 ? bump csp package thermal resistance, junction ? to ? air (note 3) thermal resistance, junction ? to ? air (note 4) r ja 90 157 c/w 3. specified according to jedec 51.7 4 ? layer board. 4. single component mounted on 4 ? layer board, 480 mm 2 , top layer thickness: 1 oz, cu area: 100 mm 2 . table 4. electrical characteristics ? 40 c t j 125 c; v in = v out(nom) + 0.3 v or 2.0 v, whichever is greater; i out = 10 ma, c in = c out = 1 f unless otherwise noted. typical values are at t j = +25 c. (note 5) parameter test conditions symbol min typ max unit operating input voltage v in 2.0 5.5 v output voltage accuracy v out + 0.3 v v in 5.5 v 0 ma i out 200 ma v out ? 2 +2 % line regulation v out + 0.3 v v in 5.5 v reg line 150 v/v load regulation i out = 0 ma to 200 ma reg load 2 v/ma dropout voltage (note 6) v do = v in ? (v out(nom) ? 100 mv) i out = 200 ma v out = 1.8 v v out = 2.5 v v out = 2.6 v v out = 2.8 v v out = 2.85 v v out = 3.0 v v out = 3.3 v v do 170 100 90 80 80 70 65 220 140 130 120 120 110 100 mv quiescent current i out = 0 ma i q 35 50 a ground current i out = 200 ma v out < 1.8 v v out 1.8 v i gnd 255 155 300 200 a disable current v en = 0 v i dis 0.3 1 a output current limit v out = v out(nom) ? 100 mv i out 250 400 530 ma output short circuit current v out = 0 v i sc 250 400 530 ma en pin threshold voltage high threshold low threshold v en voltage increasing v en voltage decreasing v en_hi v en_lo 0.9 0.4 v en pin input current v en = 5.5 v i en 100 500 na turn ? on time v out = 0 v to 98% v out(nom) , after assertion of the en t on 150 s power supply rejection ratio v in = 3.8 v, v out = 3.3 v v pp = 100 mv i out = 200 ma f = 100 hz f = 1 khz f = 10 khz psrr 74 72 56 db output noise voltage v out = 1.8 v, i out = 200 ma f = 100 hz to 100 khz v n 10 v rms line transient v out + 0.3 v v in v out + 1.3 v or v out + 0.3 v v in v out + 1.3 v in 1 s 20 mv load transient i out = 1 ma to 200 ma or i out = 200 ma to 1 ma in 1 s v out 80 mv undervoltage lock ? out v in rising from 0 v to 5.5 v uvlo 1.3 1.6 1.9 v thermal shutdown temperat- ure temperature increasing from t j = +25 c t sd 165 c thermal shutdown hysteresis temperature falling from t sd t sdh ? 20 ? c 5. performance guaranteed over the indicated operating temperature range by design and/or characterization production tested at t j = t a = 25 c. low duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible . 6. characterized when v out falls 100 mv below the regulated voltage at v in = v out(nom) + 0.3 v.
ncp729 http://onsemi.com 4 typical characteristics figure 3. output voltage noise, v out = 0.8 v, c out = 1 f figure 4. output voltage noise, v out = 3.3 v, c out = 1 f frequency (hz) frequency (hz) 10 m 1 m 100 k 10 k 1 k 100 10 0.001 0.01 0.1 1 10 10 m 1 m 100 k 10 k 1 k 100 10 0.001 0.01 0.1 1 10 figure 5. psrr, v out = 1.8 v, c out = 1 f figure 6. psrr, v out = 2.8 v, c out = 1 f frequency (hz) frequency (hz) 10 m 1 m 100 k 10 k 1 k 100 10 0 10 20 30 40 60 70 80 10 m 1 m 100 k 10 k 1 k 100 10 0 10 20 40 50 60 80 90 figure 7. psrr, v out = 3.3 v, c out = 1 f figure 8. psrr, v out = 3.3 v, c out = 4.7 f frequency (hz) frequency (hz) 10 m 1 m 100 k 10 k 1 k 100 10 0 10 20 40 50 60 80 90 1 m 10 m 100 k 10 k 1 k 100 10 0 10 20 40 50 60 80 90 output voltage noise ( v/rthz) output voltage noise ( v/rthz) psrr (db) psrr (db) psrr (db) psrr (db) 50 30 70 30 70 30 70 i out = 10 ma v in = 2.0 v, v out = 0.8 v, c in = c out = 1 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 10 ma v in = 3.6 v, v out = 3.3 v, c in = c out = 1 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 10 ma v in = 2.3 v, v out = 1.8 v, c in = none, c out = 1 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 100 ma i out = 10 ma v in = 3.3 v, v out = 2.8 v, c in = none, c out = 1 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 100 ma i out = 10 ma v in = 3.8 v, v out = 3.3 v, c in = none, c out = 1 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 100 ma i out = 10 ma v in = 3.8 v, v out = 3.3 v, c in = none, c out = 4.7 f, t a = 25 c i out = 200 ma i out = 1 ma i out = 100 ma
ncp729 http://onsemi.com 5 typical characteristics figure 9. ground current vs. output current, v out = 0.8 v figure 10. ground current vs. output current, v out = 3.3 v output current (ma) output current (ma) 1000 100 10 1 0.1 0.01 0.001 0 40 80 120 160 200 240 280 1000 100 10 1 0.1 0.01 0.001 0 20 60 80 100 140 180 200 figure 11. quiescent current vs. input voltage, v out = 0.8 v figure 12. quiescent current vs. input voltage, v out = 3.3 v input voltage (v) input voltage (v) 5.0 4.5 5.5 4.0 3.5 3.0 2.5 2.0 20 25 30 35 40 45 50 figure 13. dropout voltage vs. output current, v out = 1.8 v figure 14. dropout voltage vs. output current, v out = 2.8 v output current (ma) output current (ma) 175 150 125 100 75 50 25 0 0 20 60 80 120 160 180 220 175 150 125 100 75 50 25 0 40 50 60 70 80 90 110 120 ground current ( a) ground current ( a) quiescent current ( a) quiescent current ( a) dropout voltage (mv) dropout voltage (mv) 200 100 t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out(nom) = 2.8 v t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out(nom) = 1.8 v 40 100 140 200 t a = 125 c t a = 25 c t a = ? 40 c 200 c in = 1 f, c out = 1 f, v out(nom) = 0.8 v, i out = 0 ma 5.0 4.5 5.5 4.0 3.5 3.0 2.5 2.0 10 25 30 35 40 45 50 t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out(nom) = 3.3 v, i out = 0 ma t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out = 0.8 v, v in = 2.0 v 20 60 100 140 180 220 260 t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out = 3.3 v, v in = 3.6 v 40 120 160 20 15
ncp729 http://onsemi.com 6 typical characteristics figure 15. dropout voltage vs. output current, v out = 3.3 v figure 16. output voltage vs. temperature, v out = 0.8 v output current (ma) junction temperature ( c) 175 150 125 100 75 50 25 0 40 50 60 70 80 100 110 120 100 80 60 40 20 0 ? 20 ? 40 0.780 0.785 0.790 0.795 0.805 0.810 0.815 0.820 figure 17. output voltage vs. temperature, v out = 1.8 v figure 18. output voltage vs. temperature, v out = 3.3 v junction temperature ( c) junction temperature ( c) figure 19. load regulation vs. temperature figure 20. line regulation vs. temperature junction temperature ( c) junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 ? 3 ? 2 ? 1 0 1 2 3 dropout voltage (mv) output voltage (v) output voltage (v) output voltage (v) output voltage deviation (mv) output voltage deviation (mv) 200 90 t a = 125 c t a = 25 c t a = ? 40 c c in = 1 f, c out = 1 f, v out(nom) = 3.3 v 0.800 120 140 v out = 0.8 v, c out = c in = 1 f, i out = 10 ma v in = 5.5 v v in = 2.0 v 100 80 60 40 20 0 ? 20 ? 40 1.760 1.770 1.780 1.790 1.810 1.820 1.830 1.840 1.800 120 140 v out = 1.8 v, c out = c in = 1 f, i out = 10 ma v in = 5.5 v v in = 2.1 v 100 80 60 40 20 0 ? 20 ? 40 3.260 3.270 3.280 3.290 3.310 3.320 3.330 3.340 3.300 120 140 v out = 3.3 v, c out = c in = 1 f, i out = 10 ma v in = 5.5 v v in = 3.6 v 120 140 v in = 2.0 v or v out(nom) + 0.3 v, c out = c in = 1 f, i out = 0 ma to 200 ma v out = 0.8 v v out = 3.3 v 100 80 60 40 20 0 ? 20 ? 40 0 1 2 3 4 5 6 120 140 v in = 2.0 v or v out(nom) + 0.3 v to 5.5 v, c out = c in = 1 f, i out = 10 ma v out = 0.8 v v out = 3.3 v
ncp729 http://onsemi.com 7 typical characteristics figure 21. output current limit vs. temperature figure 22. short circuit current vs. temperature junction temperature ( c) junction temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 300 350 400 450 500 550 figure 23. shutdown current vs. temperature figure 24. enable input current vs. enable voltage junction temperature ( c) enable voltage (v) 0 0.2 0.4 0.6 0.8 1.0 6 5 4 3 2 1 0 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 figure 25. enable threshold vs. temperature figure 26. uvlo threshold vs. temperature junction temperature ( c) junction temperature ( c) 120 100 60 40 20 0 ? 20 ? 40 0 0.2 0.4 0.6 0.8 1.0 1.2 120 80 60 40 20 0 ? 20 ? 40 1.0 1.2 1.4 1.6 1.8 2.0 output current limit (ma) short circuit current (ma) shutdown current ( a) enable input current ( a) enable threshold (v) uvlo threshold (v) 120 140 v in = 2.0 v or v out(nom) + 0.3 v, c out = c in = 1 f, v out = v out(nom) ? 100 mv v out(nom) = 3.3 v v out(nom) = 0.8 v 100 80 60 40 20 0 ? 20 ? 40 300 350 400 450 500 550 120 140 v in = 2.0 v or v out(nom) + 0.3 v, c out = c in = 1 f, v out = 0 v (shorted to gnd) v out(nom) = 3.3 v v out(nom) = 0.8 v 100 80 60 40 20 0 ? 20 ? 40 120 140 v in = 5.5 v, c out = c in = 1 f, v en = 0 v v out(nom) = 3.3 v v out(nom) = 0.8 v t a = 125 c t a = 25 c t a = ? 40 c v in = 3.6 v, v out(nom) = 3.3 v, c out = c in = 1 f, i out = 10 ma 80 140 v in = 3.6 v, v out = 3.3 v, c out = c in = 1 f, i out = 10 ma v en rising v en falling v in rising v in falling 100 140 v en = v in , v out = 3.3 v, c out = c in = 1 f, i out = 10 ma
ncp729 http://onsemi.com 8 typical characteristics figure 27. turn ? on response, v out = 2.8 v figure 28. turn ? on response, v out = 1.8 v 100 s/div 100 s/div figure 29. turn ? off response, v out = 2.8 v figure 30. turn ? off response, v out = 1.8 v 2 ms/div 2 ms/div figure 31. load transient response, v out = 2.8 v, i out = 1 ma to 200 ma figure 32. load transient response, v out = 1.8 v, i out = 1 ma to 200 ma 50 s/div 50 s/div 1 v/div 1 v/div 1 v/div 0 v 0 v 0 ma v out v en i inrush v in = 3.3 v v out(nom) = 2.8 v c in = c out = 1 f i out = 1 ma t a = 25 c 200 ma/div 500 mv/div 200 ma/div 0 v 0 v 0 ma v out v en i inrush v in = 2.3 v v out(nom) = 1.8 v c in = c out = 1 f i out = 1 ma t a = 25 c 1 v/div 1 v/div 1 v/div 0 v 0 v v out v en v in = 3.3 v v out(nom) = 2.8 v c in = c out = 1 f i out = 1 ma t a = 25 c 500 mv/div 0 v 0 v v out v en v in = 2.3 v v out(nom) = 1.8 v c in = c out = 1 f i out = 1 ma t a = 25 c 200 ma/div 100 mv/div i out = 200 ma v in = 3.3 v v out(nom) = 2.8 v c in = c out = 1 f i out = 1 ma ... 200 ma i out / t = 200 ma/1 s t a = 25 c i out = 1 ma v out = 2.8 v 200 ma/div 100 mv/div i out = 200 ma v in = 2.3 v v out(nom) = 1.8 v c in = c out = 1 f i out = 1 ma ... 200 ma i out / t = 200 ma/1 s t a = 25 c i out = 1 ma v out = 1.8 v
ncp729 http://onsemi.com 9 typical characteristics 200 ma/div 100 mv/div figure 33. load transient response, v out = 2.8 v, i out = 10 ma to 200 ma figure 34. load transient response, v out = 1.8 v, i out = 10 ma to 200 ma 20 s/div 20 s/div figure 35. short ? circuit response, v out = 2.8 v figure 36. short ? circuit response, v out = 1.8 v 200 s/div 100 s/div figure 37. line transient response, v out = 2.8 v figure 38. line transient response, v out = 1.8 v 200 s/div 200 s/div i out = 200 ma v in = 3.3 v v out(nom) = 2.8 v c in = c out = 1 f i out = 10 ma ... 200 ma i out / t = 200 ma/1 s t a = 25 c i out = 10 ma v out = 2.8 v 200 ma/div 100 mv/div i out = 200 ma v in = 2.3 v v out(nom) = 1.8 v c in = c out = 1 f i out = 10 ma ... 200 ma i out / t = 200 ma/1 s t a = 25 c i out = 10 ma v out = 1.8 v 300 ma/div 1 v/div v in = 3.3 v v out(nom) = 2.8 v c in = c out = 1 f v out = 2.8 v to 0 v t a = 25 c 1 ma v out = 2.8 v 300 ma/div 500 mv/div i short 0 v v in = 2.3 v v out(nom) = 1.8 v c in = c out = 1 f v out = 1.8 v to 0 v t a = 25 c 1 ma v out = 1.8 v i short 0 v 40 mv/div 500 mv/div v out = 2.8 v v in = 3.3 v to 4.3 v v in / t = 1 v/1 s v out(nom) = 2.8 v c out = 1 f i out = 10 ma v in = 3.3 v 40 mv/div 500 mv/div v in = 4.3 v v out = 1.8 v v in = 2.3 v to 3.3 v v in / t = 1 v/1 s v out(nom) = 1.8 v c out = 1 f i out = 10 ma v in = 2.3 v v in = 3.3 v
ncp729 http://onsemi.com 10 typical characteristics figure 39. esr vs. output current i out , output current (ma) 100 80 60 40 20 0 0.001 0.01 0.1 1 10 esr ( ) 120 200 v in = v out(nom) + 0.3 v or 2 v, c out = c in = 1 f, t a = 25 c v out = 3.3 v 140 160 180 v out = 0.8 v unstable operation region stable operation region
ncp729 http://onsemi.com 11 applications information general the ncp729 is a high performance 200 ma very low dropout linear regulator. this device delivers excellent noise and dynamic performance. it features typical quiescent current of 35 a at no ? load, ultra ? low noise of 10 v rms and high psrr of 72 db at 1 khz. such excellent dynamic parameters and small package size make the device an ideal choice for powering the precision analog and noise sensitive circuitry in portable applications. ncp729 requires very small voltage headroom for correct operation. the dropout for 3.3 v voltage option is only 68 mv (typ.) a logic en input provides on/off control of the output voltage. when the en is low the device consumes as low as typ. 300 na from the in pin. the device is fully protected in case of output overload, output short circuit condition and overheating, assuring a very robust design. input capacitor (c in ) it is recommended to connect a minimum of 1 f ceramic x5r or x7r capacitor close to the in pin of the device. this capacitor will provide a low impedance path for unwanted ac signals or noise modulated onto constant input voltage. there is no requirement for the min./max. esr of the input capacitor but it is recommended to use ceramic capacitors for their low esr and esl. a good input capacitor will limit the influence of input trace inductance and power source resistance during sudden load current changes. lar ger input capacitor may be necessary if fast and large line/load transients are encountered in the application. output capacitor (c out ) the ncp729 is designed to operate with a small 1.0 f ceramic capacitor on the output. to assure proper operation it is recommended to use min. 1.0 f capacitor with the initial tolerance of 10%, made of x7r or x5r dielectric material types. ncp729 is internally compensated so there is no requirement for the minimum value of equivalent series resistance (esr) for the c out but the maximum value of esr should be less than 500 m . larger output capacitors could be used to improve the load transient response or high frequency psrr. this part is not designed to work with tantalum or electrolytic capacitors on the output due to their large esr and esl. the equivalent series resistance of tantalum capacitors is also strongly dependent on the temperature, increasing at low temperatures. the tantalum capacitors are generally more costly than ceramic capacitors. the table below lists examples of suitable output capacitors: part number description c0402c105k8pactu 1 f ceramic 10%, 10 v, 0402, x5r c1005x5r1a105k -||- GRM155R61A105KE15D -||- 0402zd105kat2a -||- mcca000571 1 f ceramic 10%, 50 v, 1206, x7r ecj ? 0eb0j475m 4.7 f ceramic 20%, 6.3 v, 0402, x5r no ? load operation the regulator remains stable and regulates the output voltage properly within the 2% tolerance limits with no external load applied to the output. enable operation the ncp729 uses the en pin to enable, disable its output and to deactivate, activate the active output discharge function. if the en pin voltage is <0.4 v the device is guaranteed to be disabled. the pass transistor is turned ? off and the active discharge transistor is active so that the output voltage v out is pulled to gnd through a 1 k resistor. in the disable state the device consumes as low as typ. 300 na from the v in . if the en pin voltage > 0.9 v the device is guaranteed to be enabled. the output voltage is regulated at the nominal value and the active discharge transistor is turned ? off. the en pin has internal pull ? down current source with typ. value of 110 na which assures that the device is turned ? off when the en pin is not connected. a build in 2 mv of hysteresis in the en prevents from periodic on/off oscillations that can occur due to noise. in the case where the en function isn?t required the en pin should be tied directly to in. undervoltage lockout the internal uvlo circuitry assures that the device becomes disabled when the v in falls below typ. 1.5 v. when the v in voltage ramps ? up the ncp729 becomes enabled for v in 1.6 v. the 100 mv hysteresis prevents from on/off oscillations that can occur due to noise on v in line. reverse current the pmos pass transistor has an inherent body diode which will be forward biased in the case that v out > v in . due to this fact in cases where the extended reverse current condition is anticipated the device may require additional external protection.
ncp729 http://onsemi.com 12 output current limit output current is internally limited within the ic to a typical 400 ma. the ncp729 will source this amount of current measured with the output voltage 100 mv lower than the nominal v out . the short circuit current flowing to the in pin when the output v oltage is directly shorted to ground will be just slightly above 400 ma ? typ . 410 ma. the current limit and short circuit were verified to work properly and to secure the part from the damage up to v in = 5.5 v at t a = 25 c. there is no limitation for the short circuit duration. thermal shutdown when the die temperature exceeds the thermal shutdown threshold (t sd ? 165 c typical), thermal shutdown event is detected and the device is disabled. the ic will remain in this state until the die temperature decreases below the thermal shutdown reset threshold (t sdu ? 140 c typical). once the ic temperature falls below the 140 c the ldo is enabled. the thermal shutdown feature provides protection from a catastrophic device failure due to accidental overheating. this protection is not intended to be used as a substitute for proper heat sinking. power dissipation as power dissipated in the ncp729 increases, it might become necessary to provide some thermal relief. the maximum power dissipation supported by the device is dependent upon board design and layout. mounting pad configuration on the pcb, the board material, and the ambient temperature affect the rate of junction temperature rise for the part. the maximum power dissipation the ic can handle is given by: p d(max) t j(max) t a ja (eq. 1) the power dissipated by the ncp729 for given application conditions can be calculated from the following equations: p d v in i gnd @i out i out v in v out (eq. 2) load regulation the ncp729 features excellent load regulation of typical 200 v in the 0 ma to 200 ma range. due to this fact at large load currents the major contributors to the output voltage shift will be the junction temperature increase and the pcb trace resistance. line regulation the ic features very good line regulation of typical 150 v/v measured for the input voltage change from v in = v out + 0.3 v to 5.5 v. power supply rejection ratio the ncp729 features very good power supply rejection ratio. if desired the psrr at higher frequencies in the range 100 khz ? 10 mhz can be tuned by the selection of c out capacitor and proper pcb layout. additional ferrite bead input filter will further improve the psrr. output noise the ic is designed for ultra ? low noise output voltage. figures 3 and 4 illustrate the noise performance for dif ferent v out , i out , c out . generally the noise performance in the indicated frequency range improves with increasing output current. pcb layout recommendations to obtain good transient performance and good regulation characteristics place c in and c out capacitors close to the device pins and make the pcb traces wide. v out , v in and gnd printed circuit board traces should be as wide as possible. when the impedance of these traces is high, there is a chance for noise pickup. in order to minimize the solution size use 0402 capacitors. larger copper area connected to the pins will improve the device thermal resistance. the actual power dissipation can be calculated by the formula given in equation 2. table 5. ordering information device voltage option marking package shipping ? ncp729fc08t2g 0.8v 7aa csp4 5000 / tape & reel ncp729fc18t2g 1.8v 7ab ncp729fc25t2g 2.5v 7ag ncp729fc26t2g 2.6v 7ac ncp729fc28t2g 2.8v 7ad ncp729fc285t2g 2.85v 7ae ncp729fc30t2g 3.0v 7ah ncp729fc33t2g 3.3v 7af ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp729 http://onsemi.com 13 package dimensions csp4, 1.06x1.06 case 568ad issue a seating plane 0.10 c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. coplanarity applies to spherical crowns of solder balls. 2x dim a min max ??? millimeters a1 d 1.06 bsc e b 0.30 0.34 e 0.50 bsc 0.70 d e a b pin a1 reference e a 0.05 b c 0.03 c 0.05 c 4x b 12 b a 0.10 c a a1 c 0.21 0.26 1.06 bsc 0.10 c 2x top view side view bottom view note 3 e pitch 0.275 4x dimensions: millimeters *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 0.50 recommended a1 package outline 4x e/2 e/2 0.25 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp729/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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